A conventional synthesizer carrying out temperature compensation of a reference oscillator is described hereinafter with reference to FIG. 14, which is disclosed in, for example, Patent Document 1.
FIG. 14 is a block diagram showing a conventional synthesizer carrying out temperature compensation of a reference oscillator. In conventional synthesizer 100 shown in FIG. 14, a reference oscillation signal output from reference frequency oscillator 101 is divided by first frequency divider 102, and then input into comparator 103. Furthermore, an output signal from comparator 103 is integrated in low-pass filter 104, and converted into a signal having a frequency near a direct current. Based on a voltage value of this signal, voltage control oscillator 105 outputs an oscillation signal as a local signal. Furthermore, voltage control oscillator 105 inputs an oscillation signal into second frequency divider 106. Second frequency divider 106 divides a frequency of the oscillation signal by a frequency division number designated by control circuit 107 according to channel designation, and outputs a signal into comparator 103. Comparator 103 compares the signal input from second frequency divider 106 with the signal input from first frequency divider 102.
The above-mentioned operation is an operation of a basic synthesizer. In synthesizer 100 shown in FIG. 14, the frequency division number of second frequency divider 106 is controlled by a temperature sensed by temperature sensor 108. The operation thereof is described briefly. Temperature sensor 108 detects an ambient temperature. The temperature is converted into a digital signal by A/D (analog/digital) converter 109. A predetermined correction value according to an output from A/D converter 109 is read out from memory 110 such as EEPROM (Electrically Erasable Programmable Read Only Memory) storing temperature-corrected values in advance, and is output to control circuit 107. Control circuit 107 changes the frequency division number of second frequency divider 106 according to the correction value output from memory 110.
Second frequency divider 106 includes an accumulator. A frequency division number is changed by inputting a frequency division number into the accumulator. FIG. 15 is a configuration diagram showing a conventional accumulator in second frequency divider 106. With reference to FIG. 15, a conventional method of changing a frequency division number is described by using a 19-bit binary accumulator as an example.
In FIG. 15, conventional accumulator 111 includes first flip-flop 113 for temporarily holding fractional frequency division number N data input from control circuit 107 (see FIG. 14) and transmitting the fractional frequency division number N data to adder 112 from Q terminal on the rising edge of a clock signal. Furthermore, accumulator 111 includes first flip-flop 114 for temporarily holding cumulative addition value data input from first adder 112 and transmitting the cumulative addition value data to first adder 112 from Q terminal on the rising edge of the clock signal. When a result of addition of input data from first flip-flop 113 and second flip-flop 114 in first adder 112 is an overflow, “1” as overflow data is transmitted to a second adder (not shown) constituting second frequency divider 106 (see, FIG. 14). That is to say, only when accumulator 111 in FIG. 15 outputs overflow data, a frequency division ratio of variable frequency divider 15 (see FIG. 14) is M+1, and at other time, the frequency division ratio is M.
In a conventional general synthesizer having such a configuration, when a frequency division ratio is changed, once second frequency divider 106 is reset, and then a desired frequency division ratio is selected. That is to say, as shown in FIG. 15, when reset section 115 is connected to D terminal of second flip-flop 114 and frequency division ratio is changed, firstly, a reset signal is input into R terminal of reset section 115. Thus, data stored in accumulator 111 are returned to preset data. This is because past data are stored in accumulator 111, unless such data are reset, switching to a desired frequency division ratio may be delayed. For example, when the fractional frequency division number is 219 and an operation frequency of the accumulator is 5 MHz, when the frequency division ratio is changed without carrying out reset (in a state in which the past cumulative addition value is kept), switching delay of 0.1 seconds at maximum may occur. Thus, the initial value of accumulator 111 is required to be reset to a preset value.
FIG. 16 is a timing chart showing an operation of second frequency divider 106 (see FIG. 14). For easy description, the timing chart of FIG. 16 shows an example in which a 3-bit binary accumulator is used. When fractional frequency division number N is 3, at the third rising of clock signal a, cumulative addition value b reaches 9, that is, is beyond “8” as the maximum value of 3-bit binary, so that a carry occurs. Then, “1” as overflow data c is transmitted and frequency division ratio d becomes “M+1.” At this time, “1” as remaining data after the carry is input into first flip-flop 113 (see FIG. 15). Herein, when fractional frequency division number N input from control circuit 107 is changed from “3” to the other value, in a conventional accumulator 111 shown in FIG. 15, a reset signal is input into reset section 115 and the cumulative addition value to be input into second flip-flop 114 is returned to 0. Thus, reset is carried out.
In general, conventional synthesizers are often used in channel switching of portable telephones. However, when conventional synthesizer 100 is used for receivers of digital television, and the like, at every timing second frequency divider 106 is controlled corresponding to temperature change, second frequency divider 106 may be reset. At this moment, the oscillating frequency of oscillator 105 (the output frequency of a synthesizer) is changed largely. As a result, a phase noise that is a ratio of electric power of the oscillating frequency to a noise in the vicinity thereof may be large. Since the oscillating frequency is generally used for a local signal and the like, deterioration of phase noise performance of the local signal may cause considerable deterioration of a C/N (Carrier/Noise) property of a received signal. Herein, the C/N means a ratio of a received signal to a noise. Reduction of the C/N may cause an increase in BER (Bit Error Rate) at the demodulation side, thus deteriorating the reception state. In televisions, for example, the deterioration of the C/N makes the reception state bad or makes the reception itself impossible.    Patent document 1: Japanese Patent Unexamined Publication No. H3-209917